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etrontech em6a8160 etron technology, inc. no. 6, technology rd. v, hsinchu science park, hsinchu, taiwan 30078, r.o.c. tel: (886)-3-5782345 fax: (886)-3-5778671 etron technology, inc. reserves the right to change products or specific ation without notice. 4m x 16 ddr synchronous dram (sdram) preliminary (rev. 1.1, oct. /2015) features ? fast clock rate: 200/250 mhz ? differential clock ck & ck ? bi-directional dqs ? dll enable/disable by emrs ? fully synchronous operation ? internal pipeline architecture ? four internal banks, 1m x 16-bit for each bank ? programmable mode and extended mode registers - cas latency: 2, 2.5, 3 - burst length: 2, 4, 8 - burst type: sequential & interleaved ? individual byte writes mask control ? dm write latency = 0 ? auto refresh and self refresh ? 4096 refresh cycles / 64ms ? precharge & active power down ? power supplies: v dd & v ddq = 2.5v 0.2v ? operating temperature: t a = 0~70 c ? interface: sstl_2 i/o interface ? package: 66 pin tsop ii, 0.65mm pin pitch - pb free and halogen free ? package: 60-ball, 8x13x1.2 mm (max) fbga - pb free and halogen free overview the em6a8160 sdram is a high-speed cmos double data rate synchronous dram containing 64 mbits. it is internally configured as a quad 1m x 16 dram with a synchronous interface (all signals are registered on the positive edge of the clock signal, ck). data outputs occur at both rising edges of ck and ck . read and write accesses to the sdram are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. accesses begin with the registration of a bankactivate command which is then followed by a read or write command. the em6a8160 provides programmable read or write burst lengths of 2, 4, 8. an auto precharge function may be enabled to provide a self-timed row precharge that is initiat ed at the end of the burst sequence. the refresh functions , either auto or self refresh are easy to use. in addition, em6a8160 features programmable d ll option. by having a programmable mode register and extended mode register, the system can choose the most suitable modes to maximize its performance. these devices are well suited for applications requiring high memory bandwidth and high performance. table 1. ordering information ts: indicates tsop ii package bk: indicates 8x13x1.2mm fbga package c: indicates generation code g: indicates pb and halogen free for tsopii package h: indicates pb and halogen free for fbga package part number clock frequency data rate power supply package em6a8160tsc-4g 250mhz 500mbps/pin v dd 2.5v, v ddq 2.5v tsopii em6a8160tsc-5g 200mhz 400mbps/pin v dd 2.5v, v ddq 2.5v tsopii em6a8160bkc-4h 250mhz 500mbps/pin v dd 2.5v, v ddq 2.5v fbga EM6A8160BKC-5H 200mhz 400mbps/pin v dd 2.5v, v ddq 2.5v fbga
etrontech em6a8160 rev. 1.1 2 oct. /2015 figure 1. pin assignment (top view) vssq 166 vdd vss 265 dq0 dq15 364 vddq vssq 463 dq1 dq14 562 dq2 dq13 661 vssq vddq 760 dq3 dq12 859 dq4 dq11 958 vddq vssq 10 57 dq5 dq10 11 56 dq6 dq9 12 55 vssq vddq 13 54 dq7 dq8 14 53 nc nc 15 52 vddq 16 51 ldqs udqs 18 49 vdd vref 19 48 nc vss 20 47 ldm udm 22 45 cas ck 23 44 ras cke 24 43 cs nc 25 42 nc nc 26 41 ba0 a11 27 40 ba1 a9 28 39 a10/ap a8 29 38 a0 a7 17 50 nc nc 21 46 we ck 31 36 a2 a5 32 35 a3 a4 33 34 vdd vss 30 37 a1 a6 figure 1.1 ball assignment (top view) n a b c d e f g h j 123 789 vssq dq15 dq14 vddq dq12 vssq dq10 vddq dq8 vssq vref vss ck nc a11 vss dq13 dq11 dq9 udqs udqm ck cke a9 vdd dq0 dq2 vssq dq4 vddq dq6 vssq ldqs vddq ldqm vdd we cas ras cs ba1 ba0 vddq dq1 dq3 dq5 dq7 nc a8 a6 a4 a7 a5 vss a0 a10 a2 a1 vdd a3 k l m
etrontech em6a8160 rev. 1.1 3 oct. /2015 figure 2. block diagram ck cke cs ras cas we dll clock buffer command decoder column counter control signal generator address buffer refresh counter 1m x 16 cell array (bank #0) row decoder 1m x 16 cell array (bank #1) row decoder 1m x 16 cell array (bank #2) row decoder 1m x 16 cell array (bank #3) row decoder column decoder column decoder column decoder column decoder mode register a10/ap a9 a11 ba0 ba1 ~ a0 ck data strobe buffer ldqs udqs dq buffer ldm udm dq15 dq0 ~
etrontech em6a8160 rev. 1.1 4 oct. /2015 pin descriptions table 2. pin details symbol type description ck, ck input differential clock: ck and ck are differential clock inputs. all address and control input signals are sampled on the crossi ng of the positive edge of ck and negative edge of ck . input and output data is refer enced to the crossing of ck and ck (both directions of the crossing) cke input clock enable: cke activates (high) and deactivates (low) the ck signal. if cke goes low synchronously with clock, the in ternal clock is suspended from the next clock cycle and the state of output and burst address is frozen as long as the cke remains low. when all banks are in the idle state, deactivating the clock controls the entry to the power down and self refresh modes. ba0, ba1 input bank activate: ba0 and ba1 define to which bank t he bankactivate, read, write, or bankprecharge command is being applied. a0-a11 input address inputs: a0- a 11 are sampled during the bankactivate command (row address a0-a11) and read/write command (col umn address a0-a7 with a10 defining auto precharge). cs input chip select: cs enables (sampled low) and disables (sampled high) the command decoder. all commands are masked when cs is sampled high. cs provides for external bank selection on systems with multiple banks. it is considered part of the command code. ras input row address strobe: the ras signal defines the operation commands in conjunction with the cas and we signals and is latched at the positive edges of ck. when ras and cs are asserted "low" and cas is asserted "high," either the bankactivate command or the pr echarge command is selected by the we signal. when the we is asserted "high," the bankactivate command is selected and the bank designated by ba is turned on to the active state. when the we is asserted "low," the precharge command is selected and the bank designated by ba is switched to the idle state after the precharge operation. cas input column address strobe: the cas signal defines the operation commands in conjunction with the ras and we signals and is latched at the positive edges of ck. when ras is held "high" and cs is asserted "low," the column access is started by asserting cas "low." then, the read or write command is selected by asserting we "high " or low"." we input write enable: the we signal defines the operation commands in conjunction with the ras and cas signals and is latched at the positive edges of ck. the we input is used to select the bankactivate or precharge command and read or write command. ldqs, udqs input / output bidirectional data strobe: specifies timing for input and output data. read data strobe is edge triggered. write data strobe provides a setup and hold time for data and dqm. ldqs is for dq0~7, udqs is for dq8~15. ldm, udm input data input mask: input data is masked when dm is sampled high during a write cycle. ldm masks dq0-dq7, udm masks dq8-dq15. dq0 - dq15 input / output data i/o: the dq0-dq15 input and output data ar e synchronized with positive and negative edges of ldqs & udqs. the i/o s are byte-maskable during writes. v dd supply power supply: +2.5v 0.2v
etrontech em6a8160 rev. 1.1 5 oct. /2015 v ss supply ground v ddq supply dq power: +2.5v 0.2v. provide isolated power to dqs for improved noise immunity. v ssq supply dq ground: provide isolated ground to dqs for improved noise immunity. v ref supply reference voltage for inputs: +0.5*v ddq nc - no connect: no internal connection, these pins suggest to be left unconnected.
etrontech em6a8160 rev. 1.1 6 oct. /2015 operation mode table 3 shows the truth table for the operation commands. table 3. truth table (note (1), (2)) command state cke n-1 cke n dm ba 0,1 a 10 a 0-9,11 cs ras cas we bankactivate idle (3) h x x v row address l l h h bankprecharge any h x x v l x l l h l prechargeall any h x x x h x l l h l write active (3) h x x v l l h l l write and autoprecharge active (3) h x x v h column address (a0 ~ a7) l h l l read active (3) h x x v l l h l h read and autoprecharge active (3) h x x v h column address (a0 ~ a7) l h l h (extended) mode register set idle h x x op code l l l l no-operation any h x x x x x l h h h burst stop active (4) h x x x x x l h h l device deselect any h x x x x x h x x x autorefresh idle h h x x x x l l l h selfrefresh entry idle h l x x x x l l l h selfrefresh exit idle l h x x x x h x x x (selfrefresh) l h h h idle h l x x x x h x x x precharge power down mode entry l h h h any l h x x x x h x x x precharge power down mode exit (powerdown) l h h h active h l x x x x h x x x active power down mode entry l v v v any l h x x x x h x x x active power down mode exit (powerdown) l h h h data input mask disable active h x l x x x x x x x data input mask enable (5) active h x h x x x x x x x note: 1. v=valid data, x=don't care , l=low level, h=high level 2. cke n signal is input level when commands are provided. cke n-1 signal is input level one clock cycl e before the commands are provided. 3. these are states of bank designated by ba signal. 4. device state is 2, 4, 8, burst operation. 5. ldm and udm can be enabled respectively.
etrontech em6a8160 rev. 1.1 7 oct. /2015 mode register set (mrs) the mode register stores the data for controlling various operating modes of a ddr sdram. it programs cas latency, burst type, and burst length to make the ddr sdram useful for a variety of applications. the default value of the mode register is not defined; therefore the mode regi ster must be written by the user. values stored in the register will be retained until the regi ster is reprogrammed. the m ode register is written by asserting low on cs , ras , cas , we , ba1 and ba0 (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and cke should be high). the state of address pins a0~a11 and ba0, ba1 in the same cycle in which cs , ras , cas and we are asserted low is written into the mode register. a minimum of two clock cycles, tmrd, are required to complete the write operation in the mode register. the mode register is divided into various fields depending on functionality. the burst length uses a0~a2, burst type uses a3, and cas latency (read latenc y from column address) uses a4~a6. a logic 0 should be programmed to all the undefined addresses to ens ure future compatibility. reserved states should not be used to avoid unknown device operation or incompatib ility with future versions. refer to the table for specific codes for various burst l engths, burst types and cas latencies. table 4. mode register bitmap ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 0 0 t.m. cas latency bt burst length mode register a8 a7 test mode a6 a5 a4 cas latency a3 burst type a2 a1 a0 burst length 0 0 normal mode 0 0 0 reserved 0 sequential 000 reserved 1 0 dll reset 0 0 1 reserved 1 interleave 001 2 x 1 test mode 0 1 0 2 010 4 0 1 1 3 011 8 1 0 0 reserved 100 reserved ba0 mode 1 0 1 reserved 101 reserved 0 mrs 1 1 0 2.5 110 reserved 1 emrs 1 1 1 reserved 111 reserved ? burst length field (a2~a0) this field specifies the data length of column acce ss using the a2~a0 pins and selects the burst length to be 2, 4, and 8. table 5. burst length a2 a1 a0 burst length 0 0 0 reserved 0 0 1 2 0 1 0 4 0 1 1 8 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1 1 1 reserved
etrontech em6a8160 rev. 1.1 8 oct. /2015 ? addressing mode select field (a3) the addressing mode can be one of two modes, eit her interleave mode or sequential mode. both sequential mode and interleave mode suppor t burst length of 2, 4, and 8. table 6. addressing mode a3 addressing mode 0 sequential 1 interleave ? burst definition, addressing s equence of sequential and interleave mode table 7. burst address ordering start address burst length a2 a1 a0 sequential interleave x x 0 0, 1 0, 1 2 x x 1 1, 0 1, 0 x 0 0 0, 1, 2, 3 0, 1, 2, 3 x 0 1 1, 2, 3, 0 1, 0, 3, 2 x 1 0 2, 3, 0, 1 2, 3, 0, 1 4 x 1 1 3, 0, 1, 2 3, 2, 1, 0 0 0 0 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 0 0 1 1, 2, 3, 4, 5, 6, 7, 0 1, 0, 3, 2, 5, 4, 7, 6 0 1 0 2, 3, 4, 5, 6, 7, 0, 1 2, 3, 0, 1, 6, 7, 4, 5 0 1 1 3, 4, 5, 6, 7, 0, 1, 2 3, 2, 1, 0, 7, 6, 5, 4 1 0 0 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 1 0 1 5, 6, 7, 0, 1, 2, 3, 4 5, 4, 7, 6, 1, 0, 3, 2 1 1 0 6, 7, 0, 1, 2, 3, 4, 5 6, 7, 4, 5, 2, 3, 0, 1 8 1 1 1 7, 0, 1, 2, 3, 4, 5, 6 7, 6, 5, 4, 3, 2, 1, 0 ? cas latency field (a6~a4) this field specifies the number of clock cycles from the assertion of the read co mmand to the first read data. the minimum whole value of cas latency depends on the frequency of ck. the minimum whole value satisfying the following formula must be programmed into this field. t cac (min) cas latency x t ck table 8. cas latency a6 a5 a4 cas latency 0 0 0 reserved 0 0 1 reserved 0 1 0 2 clocks 0 1 1 3 clocks 1 0 0 reserved 1 0 1 reserved 1 1 0 2.5 clocks 1 1 1 reserved
etrontech em6a8160 rev. 1.1 9 oct. /2015 ? test mode field (a8~a7) these two bits are used to enter the test mode and must be programmed to "00" in normal operation. table 9. test mode a8 a7 test mode 0 0 normal mode 1 0 dll reset x 1 test mode ? (ba0, ba1) table 10. mrs/emrs ba1 ba0 a11 ~ a0 rfu 0 mrs cycle rfu 1 extended functions (emrs)
etrontech em6a8160 rev. 1.1 10 oct. /2015 extended mode register set (emrs) the extended mode register set stores the data for enab ling or disabling dll and selecting output driver strength. the default value of the ex tended mode register is not defined, t herefore must be written after power up for proper operation. the extended mode regi ster is written by asserting low on cs , ras , cas , and we . the state of a0 ~ a11, ba0 and ba1 is writt en in the mode register in the same cycle as cs , ras , cas , and we going low. (the device should have all banks idle with no bursts in progress prior to writing into the mode register, and cke should be high). a1 is used for setting dr iver strength to normal, or weak. two clock cycles are required to complete the write operation in the extended mode register. the m ode register contents can be changed using the same command and clock cycle requirem ents during operation as long as all banks are in the idle state. a0 is used for dll enable or disable. "high" on ba0 is used for emrs. refer to the table for specific codes. table 11. extended mode register bitmap ba1 ba0 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 1 rfu must be set to ?0? ds1 rfu must be set to ?0? ds0 dll extended mode register ba0 mode a6 a1 drive strength comment a0 dll 0 mrs 0 0 full 0 enable 1 emrs 0 1 weak 1 disable 1 0 rfu reserved for future 1 1 matched impedance output driver matches impedance
etrontech em6a8160 rev. 1.1 11 oct. /2015 table 12. absolute maximum rating symbol item values unit v i/o voltage on i/o pins relative to vss - 0.5 ~ v ddq + 0.5 v v dd , v ddq voltage on v dd , v ddq supply relative to vss - 1 ~ 3.6 v v in voltage on inputs relative to vss - 1 ~ 3.6 v t a ambient temperature 0 ~ 70 c t stg storage temperature - 55 ~ 150 c p d power dissipation 1 w i os short circuit output current 50 ma note: absolute maximum dc requirements contain stress ratings only. functional operation at the absolute maximum limits is not implied or guaranteed. extended exposure to maximum ratings may affect device reliability. table 13. recommended d.c. operating conditions (v dd = 2.5v 0.2v, t a = 0~70 c) symbol parameter min. max. unit v dd power supply voltage 2.3 2.7 v v ddq power supply voltage (for i/o buffer) 2.3 2.7 v v ref input reference voltage 0.49* v ddq 0.51* v ddq v v tt termination voltage v ref - 0.04 v ref + 0.04 v v ih (dc) input high voltage (dc) v ref + 0.15 v ddq + 0.3 v v il (dc) input low voltage (dc) -0.3 v ref ? 0.15 v v in (dc) input voltage level, ck and ck inputs -0.3 v ddq + 0.3 v v id (dc) input different voltage, ck and ck inputs 0.36 v ddq + 0.6 v i il input leakage current -2 2 a i oz output leakage current -5 5 a i oh output high current (v oh = 1.95v) -16.2 - ma i ol output low current (v ol = 0.35v) 16.2 - ma table 14. capacitance (v dd = 2.5v, f = 1mhz, t a = 25 c) tsop fbga tsop fbga unit symbol parameter min. max. delta pf c in1 input capacitance (ck, ck ) 2 1.5 3 2.5 0.25 pf c in2 input capacitance (all other input-only pins) 2 1.5 3 2.5 0.5 pf c i/o dm, dq, dqs input/output capacitance 4 3.5 5 4.5 0.5 pf note: these parameters are guaranteed by design, periodically sampled and are not 100% tested.
etrontech em6a8160 rev. 1.1 12 oct. /2015 table 15. d.c. characteristics (v dd = 2.5v 0.2v, t a = 0~70 c) -4 -5 parameter & test condition symbol max. unit operating current : one bank; active-precharge; t rc =t rc (min); t ck =t ck (min); dq,dm and dqs inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. idd0 55 50 ma operating current : one bank; active-read-precharge; bl=4; t rc =t rc (min); t ck =t ck (min); lout=0ma; address and control inputs changing once per clock cycle idd1 60 55 ma precharge power-down standby current: all banks idle; power-down mode; t ck =t ck (min); cke=low idd2p 4 4 ma idle standby current : cke = high; cs =high(deselect); all banks idle; t ck =t ck (min); address and control inputs changing once per clock cycle; v in =v ref for dq, dqs and dm idd2n 25 25 ma active power-down standby current : one bank active; power-down mode; cke=low; t ck =t ck (min) idd3p 17 17 ma active standby current : cs =high;cke=high; one bank active ; t rc =t rc (max);t ck =t ck (min);address and control inputs changing once per clock cycle; dq,dqs,and dm inputs changing twice per clock cycle idd3n 40 40 ma operating current burst read : bl=2; reads; continuous burst; one bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); lout=0ma;50% of data changing on every transfer idd4r 100 90 ma operating current burst write : bl=2; writes; continuous burst ;one bank active; address and control inputs changing once per clock cycle; t ck =t ck (min); dq,dqs,and dm changing twice per clock cycle; 50% of data changing on every transfer idd4w 95 85 ma auto refresh current : t rc =t rfc (min); t ck =t ck (min) idd5 65 65 ma self refresh current: self refresh mode ; cke 0.2v;t ck =t ck (min) idd6 2 2 ma burst operating current 4 bank operation: four bank interleaving reads; bl=4;with auto precharge; t rc =t rc (min); t ck =t ck (min); address and control inputs change only during active, read , or write command idd7 120 110 ma figure 3. timing waveform for idd7 measurement at 200 mhz ck operation ck ck address command t rcd act read ap act read ap act read ap act act read ap bank 0 row d bank 3 col c bank 1 row e bank 0 col d bank 2 row f bank 1 col e bank 3 row g bank 0 row h bank 2 col f ...pattern repeats... dqs dq cl=3 d0 a d0 a d0 b d0 b d0 b d0 b d0 c d0 c d0 c d0 c d0 d d0 d d0 d d0 d d0 e d0 e d0 e d0 e d0 f d0 f d0 a d0 a
etrontech em6a8160 rev. 1.1 13 oct. /2015 table 16. electrical ac characteristics (v dd = 2.5v 0.2v, t a = 0~70 c) -4 -5 symbol parameter min. max. min. max. unit cl = 2 - - 7.5 12 ns cl = 2.5 - - 6 12 ns t ck clock cycle time cl = 3 4 12 5 12 ns t ch clock high level width 0.45 0.55 0.45 0.55 t ck t cl clock low level width 0.45 0.55 0.45 0.55 t ck t dqsck dqs-out access time from ck, ck -0.6 0.6 -0.6 0.6 ns t ac output access time from ck, ck -0.7 0.7 -0.7 0.7 ns t dqsq dqs-dq skew - 0.4 - 0.4 ns t hz dq & dqs high-impedance time from ck / ck - 0.7 - 0.7 ns t lz dq & dqs low-impedance time from ck / ck -0.7 0.7 -0.7 0.7 ns t rpre read preamble 0.9 1.1 0.9 1.1 t ck t rpst read postamble 0.4 0.6 0.4 0.6 t ck t dqss ck to valid dqs-in 0.8 1.2 0.72 1.25 t ck t wpres dqs-in setup time 0 - 0 - ns t wpre dqs write preamble 0.25 - 0.25 - t ck t wpst dqs write postamble 0.4 0.6 0.4 0.6 t ck t dqsh dqs in high level pulse width 0.35 - 0.35 - t ck t dqsl dqs in low level pulse width 0.35 - 0.35 - t ck t dss dqs falling edge to ck setup time 0.2 - 0.2 - t ck t dsh dqs falling edge hold time from ck 0.2 - 0.2 - t ck t is address and control input setup time 0.7 - 0.7 - ns t ih address and control input hold time 0.7 - 0.7 - ns t ds dq & dm setup time to dqs 0.4 - 0.4 - ns t dh dq & dm hold time to dqs 0.4 - 0.4 - ns t qhs data hold skew factor - 0.5 - 0.5 ns t hp clock half period (t cl, t ch ) min - (t cl, t ch ) min - ns t qh dq/dqs output hold time from dqs t hp - t qhs - t hp - t qhs - ns t rc row cycle time 55 - 55 - ns t rfc refresh row cycle time 70 - 70 - ns t ras row active time 40 70k 40 70k ns t rcd active to read or write delay 15 - 15 - ns t rp row precharge time 15 - 15 - ns t rrd row active to row active delay 10 - 10 - ns t wr write recovery time 15 - 15 - ns t wtr internal write to read command delay 10 - 10 - ns t mrd mode register set cycle time 10 - 10 - ns t dal auto precharge write recovery + precharge time t wr + t rp - t wr + t rp - t ck t ipw control and address input pulse width 2.2 - 2.2 - ns t dipw dq & dm input pulse width (for each input) 1.75 - 1.75 - ns t xsrd self refresh exit to read command delay 200 - 200 t ck t xsnr exit self refresh to non-read command 75 - 75 - t ck t refi refresh interval time - 15.6 - 15.6 s t rap active to autoprecharge delay t rcd or t ras min - t rcd or t ras min - ns
etrontech em6a8160 rev. 1.1 14 oct. /2015 table 17. recommended a.c. operating conditions (v dd = 2.5v 0.2v, t a = 0~70 c) symbol parameter min. max. unit v ih (ac) input high voltage (ac) v ref + 0.31 - v v il (ac) input low voltage (ac) - v ref ? 0.31 v v id (ac) input different voltage, ck and ck inputs 0.7 v ddq + 0.6 v v ix (ac) input crossing point voltage, ck and ck inputs 0.5*v ddq -0.2 0.5*v ddq +0.2 v note: 1. stress greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. 2. all voltages are referenced to v ss . 3. these parameters depend on the cycle rate and these values are measured by the cycle rate under the minimum value of t ck and t rc . input signals are changed one time during t ck . 4. power-up sequence is described in note 6. 5. a.c. test conditions table 18. sstl_2 interface reference level of output signals (v ref ) 0.5 * v ddq output load reference to the test load input signal levels v ref +0.35 v / v ref -0.35 v input signals slew rate 1 v/ns reference level of input signals 0.5 * v ddq figure 4. sstl_2 a.c. test load dq, dqs z0=50 ? 50 ? 30pf 0.5 * vddq
etrontech em6a8160 rev. 1.1 15 oct. /2015 6. power up sequence power up must be performed in the following sequence. 1) apply power to v dd before or at the same time as v ddq, v tt and v ref when all input signals are held "nop" state and maintain cke ?low?. 2) start clock and maintain stable condition for minimum 200 s. 3) issue a ?nop? command and keep cke ?high? 4) issue a ?precharge all? command. 5) issue emrs ? enable dll. 6) issue mrs ? reset dll. (an additional 200 clock cycles are required to lock the dll). 7) precharge all banks of the device. 8) issue two or more auto refresh commands. 9) issue mrs ? with a8 to low to initialize the mode register. 7. for command/address slew rate 0.5v/ns and <1.0v/ns. for ck & ck slew rate 1.0v/ns.
etrontech em6a8160 rev. 1.1 16 oct. /2015 timing waveforms figure 5. activating a specifi c row in a specific bank ck ck cke cs ras cas we ra address ba ba0,1 don?t care high ra=row address ba=bank address figure 6. trcd and trrd definition ck ck address ba0,ba1 act nop command nop act nop nop rd/wr nop row row col bank a bank b bank b t rrd t rcd don?t care
etrontech em6a8160 rev. 1.1 17 oct. /2015 figure 7. read command ck ck cke cs ras cas we ca a0 - a7 a10 don?t care high en ap dis ap ba ba0,1 ca=column address ba=bank address en ap=enable autoprecharge dis ap=disable autoprecharge
etrontech em6a8160 rev. 1.1 18 oct. /2015 figure 8. read burst required cas latencies (cl=3) do n ck ck command read nop nop nop nop nop bank a, col n address dqs dq cl=3 don?t care do n=data out from column n burst length=4 3 subsequent elements of data out appear in the programmed order following do n
etrontech em6a8160 rev. 1.1 19 oct. /2015 figure 9. consecutive read bursts required cas latencies (cl=3) do o ck ck command read nop read nop nop nop bank, col n address dqs dq cl=3 don?t care bank, col o do n (or o)=data out from column n (or column o) burst length=4 or 8 (if 4, the bursts are concaten ated; if 8, the second burst interrupts the first) 3 subsequent elements of data out appear in the programmed order following do n 3 (or 7) subsequent elements of data out a ppear in the programmed order following do o read commands shown must be to the same device do n
etrontech em6a8160 rev. 1.1 20 oct. /2015 figure 10. non-consecutive read burs ts required cas latencies (cl=3) ck ck command read nop nop read nop nop bank, col n address dqs dq cl=3 don?t care bank, col o nop do n (or o)=data out from column n (or column o) burst length=4 3 subsequent elements of data out appear in the programmed order following do n (and following do o) do o do n
etrontech em6a8160 rev. 1.1 21 oct. /2015 figure 11. random read accesses required cas latencies (cl=3) do p do n' do o do o' ck ck command read read read read nop nop bank, col n address dqs dq cl=3 don?t care bank, col o bank, col p bank, col q do n, etc. =data out from column n, etc. n', etc. =the next data out following do n, etc. accord ing to the programmed burst order burst length=2,4 or 8 in cases shown. if burst of 4 or 8, the burst is interrupted reads are to active rows in any banks do n
etrontech em6a8160 rev. 1.1 22 oct. /2015 figure 12. terminating a read burst required cas latencies (cl=3) ck ck command read nop bst nop nop nop bank a, col n address dqs dq cl=3 don?t care do n = data out from column n cases shown are bursts of 8 terminated after 4 data elements 3 subsequent elements of data out appear in the programmed or der following do n do n
etrontech em6a8160 rev. 1.1 23 oct. /2015 figure 13. read to write required cas latencies (cl=3) ck ck command read bst nop nop write nop bank, col n address dqs dq cl=3 don?t care bank, col o min tdqss di o dm do n (or o)= data out from column n (or column o) burst length= 4 in the cases shown (applies for bursts of 8 as well; if burst length is 2, the bst command shown can be nop) 1 subsequent element of data out appears in the programmed order following do n data in elements are applied following di o in the programmed order do n
etrontech em6a8160 rev. 1.1 24 oct. /2015 figure 14. read to precharge required cas latencies (cl=3) ck ck command read nop pre nop nop act bank a, col n address dqs dq cl=3 don?t care bank (a or all) bank a, row t rp do n = data out from column n cases shown are either unin terrupted bursts of 4, or interrupted bursts of 8 3 subsequent elements of data ou t appear in the programmed order following do n precharge may be applied at ( bl/2) tck after the read command note that precharge may not be issu ed before tras ns after the active command for applicable banks the active command may be ap plied if trc has been met do n
etrontech em6a8160 rev. 1.1 25 oct. /2015 figure 15. write command ck ck cke cs ras cas we ca a0 - a7 a10 don?t care high en ap dis ap ba ba0,1 ca=column address ba=bank address en ap=enable autoprecharge dis ap=disable autoprecharge
etrontech em6a8160 rev. 1.1 26 oct. /2015 figure 16. write max dqss ck ck command write nop nop nop bank a, col n address dqs dq tdqss don?t care dm t0 t1 t2 t3 t4 t5 t6 t7 max di n di n = data in for column n 3 subsequent elements of data in are applied in the programmed order following di n a non-interrupted burst of 4 is shown a10 is low with the write command (auto precharge disabled)
etrontech em6a8160 rev. 1.1 27 oct. /2015 figure 17. write min dqss ck ck command write nop nop nop bank a, col n address dqs dq tdqss dm t0 t1 t2 t3 t4 t5 t6 min di n don?t care di n = data in for column n 3 subsequent elements of data in are applied in the programmed order following di n a non-interrupt ed burst of 4 is shown a10 is low with the write comma nd (auto precharge disabled)
etrontech em6a8160 rev. 1.1 28 oct. /2015 figure 18. write burst nom, min, and max tdqss ck ck command write nop nop nop bank , col n address dqs dq tdqss (nom) don?t care dm t0 t1 t2 t3 t4 t5 t6 t7 di n t8 t9 t10 t11 nop nop dqs dq tdqss (min) dm di n dqs dq tdqss (max) dm di n di n = data in for column n 3 subsequent elements of data are applied in the programmed order following di n a non-interrupted burst of 4 is shown a10 is low with the write command (auto precharge disabled) dm=udm & ldm
etrontech em6a8160 rev. 1.1 29 oct. /2015 figure 19. write to write max tdqss ck ck command write nop write nop bank , col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 nop nop dqs dq tdqss (max) dm di n bank , col o di o don?t care di n , etc. = data in for column n,etc. 3 subsequent elements of data in are a pplied in the programmed order following di n non-interrupted bursts of 4 are shown dm= udm & ldm 3 subsequent elements of data in are a pplied in the programmed order following di o
etrontech em6a8160 rev. 1.1 30 oct. /2015 figure 20. write to write max tdqss, non consecutive ck ck command write nop nop write bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 nop nop dqs dq tdqss (max) dm di n bank col o di o don?t care di n, etc. = data in for column n, etc. 3 subsequent elements of data in are applied in the programmed order following di n non-interrupted bursts of 4 are shown dm= udm & ldm 3 subsequent elements of data in are applied in the programmed order following di o
etrontech em6a8160 rev. 1.1 31 oct. /2015 figure 21. random write cycles max tdqss ck ck command write write write write bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 write dqs dq tdqss (max) dm di n bank col q di o di n' di o' di p di p' di q di q' bank col o bank col p bank col r don?t care di n, etc. = data in for column n, etc. n', etc. = the next data in following di n, etc. according to the programmed burst order if burst of 4 or 8, the burst would be truncated dm= udm & ldm programmed burst length 2, 4, or 8 in cases shown each write command may be to any bank a nd may be to the same or different devices
etrontech em6a8160 rev. 1.1 32 oct. /2015 figure 22. write to read max tdqss non interrupting ck ck command write nop nop read bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n bank col o t10 t11 nop twtr cl=3 don?t care di n, etc. = data in for column n, etc. 1 subsequent elements of data in are a pplied in the programmed order following di n twtr is referenced from the first positive ck edge after the last data in pair dm= udm & ldm a non-interrupted burst of 2 is shown a10 is low with the write command (auto precharge is disabled) the read and write commands are to the same devices but not necessar ily to the same bank t12 nop
etrontech em6a8160 rev. 1.1 33 oct. /2015 figure 23. write to read max tdqss interrupting ck ck command write nop nop read bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n bank col o t10 t11 nop twtr cl=3 don?t care di n, etc. = data in for column n, etc. 1 subsequent elements of data in are a pplied in the programmed order following di n twtr is referenced from the first positive ck edge after the last data in pair dm= udm & ldm an interrupted burst of 8 is show n, 2 data elements are written a10 is low with the write comman d (auto precharge is disabled) the read and write commands are to the same devices but not necessarily to the same bank t12
etrontech em6a8160 rev. 1.1 34 oct. /2015 figure 24. write to read max tdqss, odd number of data, interrupting ck ck write nop nop read bank col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n bank col o t10 t11 nop twtr cl=3 don?t care di n = data in for column n twtr is referenced from the first positive ck edge after the last data in pair (not the last desired data in element) dm= udm & ldm an interrupted burst of 8 is shown, 1 data elements are written a10 is low with the write comma nd (auto precharge is disabled) the read and write commands are to the same devices but not necessarily to the same bank t12 command
etrontech em6a8160 rev. 1.1 35 oct. /2015 figure 25. write to precharge max tdqss, non- interrupting ck ck command write nop nop nop bank a, col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 pre dqs dq tdqss (max) dm di n bank (a or al) t10 t11 nop twr trp don?t care di n = data in for column n 1 subsequent elements of data in are applied in the programmed order following di n twr is referenced from the first positive ck edge after the last data in pair dm= udm & ldm a non-interrupted burst of 2 is shown a10 is low with the write comma nd (auto precharge is disabled)
etrontech em6a8160 rev. 1.1 36 oct. /2015 figure 26. write to precharge max tdqss, interrupting ck ck command write nop nop pre bank a, col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n t10 t11 nop twr trp *1 *2 don?t care di n = data in for column n twr is referenced from the first positive ck edge after the last data in pair dm= udm & ldm an interrupted burst of 4 or 8 is shown, 2 data elements are written a10 is low with the write comma nd (auto precharge is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, dqs becomes don't care at this point *1 *1 *1 bank (a or all)
etrontech em6a8160 rev. 1.1 37 oct. /2015 figure 27. write to precharge max tdq ss odd number of data interrupting ck ck command write nop nop bank a, col n address t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 nop dqs dq tdqss (max) dm di n t10 t11 nop twr trp *2 don?t care di n = data in for column n twr is referenced from the first positive ck edge after the last data in pair dm= udm & ldm an interrupted burst of 4 or 8 is shown, 1 data element is written a10 is low with the write comman d (auto precharge is disabled) *1 = can be don't care for programmed burst length of 4 *2 = for programmed burst length of 4, dqs becomes don't care at this point *1 *1 *1 *1 pre bank (a or all)
etrontech em6a8160 rev. 1.1 38 oct. /2015 figure 28. precharge command ck ck cke cs ras cas we a0-a9, a11 a10 don?t care high all banks one bank ba ba0,1 ba= bank address (if a10 is low, otherwise don't care)
etrontech em6a8160 rev. 1.1 39 oct. /2015 figure 29. power-down ck ck cke valid command don?t care t0 t1 t2 t3 t4 tn tn+1 tn+2 tn+3 tn+4 valid tn+5 tn+6 nop nop no column access in progress enter power-down mode exit power-down mode t is t is figure 30. clock frequency change in precharge ck ck cmd t is t0 t1 t2 t4 tx tx+1 ty ty+1 ty+2 ty+3 ty+4 tz nop nop nop dll reset nop valid nop frequency change occurs here stable new clock before power down exit t rp minmum 2 clocks required before changing frequency 200 clocks cke
etrontech em6a8160 rev. 1.1 40 oct. /2015 figure 31. data input (write) timing dqs dq don?t care t ds di n dm t dh t ds t dh t dqsh t dqsl di n = data in for column n burst length = 4 in the case shown 3 subsequent elements of data in are applied in the programmed order following di n figure 32. data output (read) timing ck ck dq t ch t cl t qh t dqsq max t qh max t dqsq burst length = 4 in the case shown dqs
etrontech em6a8160 rev. 1.1 41 oct. /2015 figure 33. initialize and mode register sets t is t ih nop pre emrs mrs pre ar ar mrs act code code code ra tvdt>=0 t ch t cl t ck t is t ih t is t ih code code code ra t is t ih t is t ih all banks t is t ih all banks ba0=h ba1=l ba0=l ba1=l ba0=l ba1=l ba t is t ih high-z high-z lvcmos low level ck ck dm a0-a9, a11 command vref cke a10 ba0,ba1 dqs dq vdd vddq vtt (system*) *=vtt is not applied directly to the devi ce, however tvtd must be greater than or equal to zero to avoid device latch-up. ** = tmrd is required before any command can be applied, and 200 cycles of ck are required before any executable command can be applied the two auto refresh commands may be moved to follow the first mrs but precede the second precharge all command. don?t care power-up: vdd and clk stable extended mode register set load mode register, reset dll (with a8=h) 200 cycles of ck** load mode register, (with a8=l) t=200s **t mrd **t mrd t rfc t rfc **t mrd t rp
etrontech em6a8160 rev. 1.1 42 oct. /2015 figure 34. power down mode ck ck cke valid* command don?t care valid t ck nop nop enter power-down mode exit power-down mode t ch t cl t is t is t ih t is t is t ih valid t is t ih addr valid dqs dq dm no column accesses are allowed to be in progress at the time power-down is entered *=if this command is a precharge all (or if the device is already in the idle state) then the power-down mode shown is precharge power down. if this command is an active (or if at least one row is already active) then the power-down mode sh own is active power down.
etrontech em6a8160 rev. 1.1 43 oct. /2015 figure 35. auto refresh mode ck ck a0-a7 a8,a9,a11 valid nop command t is don?t care t ih nop ar nop ar nop nop act t is t ih t ch t cl t ck ra cke ra a10 ba0,ba1 dqs dq *bank(s) valid nop pre ra all banks one banks ba t ih t is dm t rp t rfc t rfc * = don't care , if a10 is high at this point; a10 must be hi gh if more than one bank is active (i.e., must precharge all acti ve banks) pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh nop commands are shown for ease of illustration ; other valid commands may be possible after trfc dm, dq and dqs signals are all don't care /high-z for operations shown
etrontech em6a8160 rev. 1.1 44 oct. /2015 figure 36. self refresh mode ck ck cke nop command don?t care valid t ck ar nop clock must be stable before exiting self refresh mode enter self refresh mode t ch t cl t is t is t ih t is t is t ih addr valid dqs dq dm t is t ih t rp* t xsnr/ t xsrd** exit self refresh mode * = device must be in the all banks idle state prior to entering self refresh mode ** = txsnr is required before any non-read command ca n be applied, and txsrd (200 cycles of ck) is required before a read command can be applied.
etrontech em6a8160 rev. 1.1 45 oct. /2015 figure 37. read without auto precharge ck ck a0-a7 nop t is t ih pre nop nop valid valid valid t is t ih t ch t cl t ck ra cke dm dqs nop read ra t ih t is dq cl=3 t rp act nop nop nop col n t is t ih ra all banks one banks bank x t is t ih dis ap *bank x bank x t rpre t dqsck min t rpst t lz t lz t ac min dqs dq t rpre t rpst t lz t lz max t dqsck t hz max t ih max max min min don?t care do n = data out from column n pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = don't care , if a10 is high at this point nop commands are shown for ease of illustration; other commands may be valid at these times precharge may not be issued before tras ns after the active command for applicable banks do n do n command a8,a9,a11 a10 ba0,ba1 max t ac case 1: t ac /t dqsck =min case 2: t ac /t dqsck =max
etrontech em6a8160 rev. 1.1 46 oct. /2015 figure 38. read with auto precharge nop t is t ih nop nop nop valid valid valid t is t ih t ch t cl t ck ra nop read ra t ih t is cl=3 t rp act nop nop nop col n t is t ih ra bank x t is t ih en ap bank x t rpre min t rpst t lz t ac min t rpre t rpst t lz t lz max t dqsck t hz max t ih min max max don?t care do n = data out from column n burst length = 4 in the case shown 3 subsequent elements of data out are provid ed in the programmed order following do n en ap = enable autoprecharge act = active, ra = row address nop commands are shown for ease of illustration; other commands may be valid at these times the read command may not be issued until trap has been satisfied. if fast autoprecharge is support ed, trap = trcd, else the rea d may not be issued prior to trasmin - (bl*tck/2) do n do n max t ac min t lz t dqsck ck ck a0-a7 command cke a10 ba0,ba1 dm dqs dq dqs dq a8,a9,a11 case 2: t ac /t dqsck =max case 1: t ac /t dqsck =min
etrontech em6a8160 rev. 1.1 47 oct. /2015 figure 39. bank read access nop t is t ih nop nop read t is t ih t ch t cl t ck nop act ra t ih t is t rc nop pre nop nop ra t is t ih col n all banks one banks dis ap bank x t rpre min t rpst t lz t lz t ac act ra ra ra ra *bank x bank x t is t ih bank x t ras t rcd t rp t dqsck min min t rpre max t lz t ac max max t rpst t dqsck don?t care do n = data out from column n pre = precharge, act = active, ra = row address, ba = bank address burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following do n dis ap = disable autoprecharge * = don't care , if a10 is high at this point nop commands are shown for ease of illustration ; other commands may be valid at these times note that trcd > trcd min so that the same timing ap plies if autoprecharge is enabled (in which case tras would be limiting) do n do n min cl=3 max t lz max t hz dq dqs case 2: t ac /t dqsck =max dq dqs case 1: t ac /t dqsck =min dm ba0,ba1 command cke ck ck a10 a8,a9,a11 a0-a7
etrontech em6a8160 rev. 1.1 48 oct. /2015 figure 40. write without auto precharge ck ck a0-a7 a8,a9,a11 nop command t is t ih nop nop nop valid t is t ih t ch t cl t ck ra cke a10 ba0,ba1 dqs nop write ra t ih t is dq t dsh pre nop nop act col n t is t ih ra all banks one banks bank x t is t ih dis ap *bank x ba t wpres case 1: t dqss =min di n t ih t dqss t dsh t dqsh t dqsl t wpst t wpre dm dqs dq t dss t wpres case 2: t dqss =max di n t dqss t dss dm t wr t rp t dqsh t wpst t dqsl t wpre don?t care di n = data in from column n pre = precharge, act = active, ra = row address, ba = bank address, ar = autorefresh burst length = 4 in the case shown 3 subsequent elements of data in are prov ided in the programmed order following di n dis ap = disable autoprecharge *= don't care , if a10 is high at this point nop commands are shown for ease of illustration; other commands may be valid at these times although tdqss is drawn only for the first dqs rising edge, each rising edge of dqs must fall within the + 25% window of the corresponding positive clock edge precharge may not be issued before tras ns after the active command for applicable banks
etrontech em6a8160 rev. 1.1 49 oct. /2015 figure 41. write with auto precharge ck ck a0-a7 a8,a9,a11 nop command t is t ih nop nop nop valid t is t ih t ch t cl t ck ra cke a10 ba0,ba1 dqs nop write ra t ih t is dq t dsh nop nop nop act col n t is t ih ra bank x dis ap ba t wpres case 1: t dqss =min di n t dqss t dsh t dqsh t dqsl t wpst t wpre dm dqs dq t dss t wpres case 2: t dqss =max di n t dqss t dss dm t dal t dqsh t wpst t dqsl valid valid t wpre don?t care di n = data in from column n burst length = 4 in the case shown 3 subsequent elements of data out are provided in the programmed order following di n en ap = enable autoprecharge act = active, ra = row address, ba = bank address nop commands are shown for ease of illustration; other commands may be valid at these times although tdqss is drawn only for the first dqs rising edge, each rising edge of dqs must fall within the + 25% window of the corresponding positive clock edge
etrontech em6a8160 rev. 1.1 50 oct. /2015 figure 42. bank write access ck ck a0-a7 a8,a9,a11 nop command t is t ih nop write nop t is t ih t ch t cl t ck cke a10 ba0,ba1 dqs nop act all banks t ih t is dq t dsh nop nop nop pre ra t is t ih bank x dis ap *bank x t wpres case 1: t dqss =min di n t dqss t dsh t dqsh t dqsl t wpst dm dqs dq case 2: t dqss =max t dqss t dss dm t ras t dqsh t wpst col n ra ra one bank t is t ih bank x t wr t rcd t wpre t dss t dqsl t wpres t wpre di n don?t care di n = data in from column n pre = precharge, act = active, ra = row address, ba = bank address burst length = 4 in the case shown 3 subsequent elements of data out are provid ed in the programmed order following di n dis ap = disable autoprecharge *= don't care , if a10 is high at this point nop commands are shown for ease of illustration ; other commands may be valid at these times although tdqss is drawn only for the first dqs rising ed ge, each rising edge of dqs must fall within the + 25% window of the correspondi ng positive clock edge precharge may not be issued before tras ns after the active command for applicable banks
etrontech em6a8160 rev. 1.1 51 oct. /2015 figure 43. write dm operation ck ck a0-a7 a8,a9,a11 nop command t is t ih nop nop nop valid t is t ih t ch t cl t ck ra cke a10 ba0,ba1 dqs nop write ra t ih t is dq t dsh pre nop nop act col n t is t ih ra all banks one banks bank x t is t ih dis ap *bank x ba t wpres case 1: t dqss =min di n t dqss t dsh t dqsh t dqsl t wpst t wpre dm dqs dq t dss t wpres case 2: t dqss =max di n t dqss t dss dm t wr t rp t dqsh t dqsl t wpre t wpst don?t care di n = data in from column n pre = precharge, act = active, ra = row address, ba = bank address burst length = 4 in the case shown 3 subsequent elements of data in are provid ed in the programmed order following di n dis ap = disable autoprecharge *= don't care , if a10 is high at this point nop commands are shown for ease of illustration ; other commands may be valid at these times although tdqss is drawn only for the first dqs rising edge, each rising edge of dqs must fall within the + 25% window of the corresponding positive clock edge precharge may not be issued before tras ns after the active command for applicable banks
etrontech em6a8160 rev. 1.1 52 oct. /2015 figure 44. 66 pin tsop ii package outline drawing information units: mm dimension in mm dimension in inch symbol min nom max min nom max a --- --- 1.2 --- --- 0.047 a1 0.05 --- 0.2 0.002 --- 0.008 a2 0.9 1.0 1.1 0.035 0.039 0.043 b 0.22 --- 0.45 0.009 --- 0.018 e --- 0.65 --- --- 0.026 --- c 0.095 0.125 0.21 0.004 0.005 0.008 d 22.09 22.22 22.35 0.87 0.875 0.88 e 10.03 10.16 10.29 0.395 0.4 0.405 he 11.56 11.76 11.96 0.455 0.463 0.471 l 0.40 0.5 0.6 0.016 0.02 0.024 l1 --- 0.8 --- --- 0.032 --- f --- 0.25 --- --- 0.01 --- 0 --- 8 0 --- 8 s --- 0.71 --- --- 0.028 --- --- --- 0.10 --- --- 0.004 d y c s b d f (typ) c e a a1 a2 e he l1 l
etrontech em6a8160 rev. 1.1 53 oct. /2015 figure 45. fbga 60ball 8x13x1.2 mm(max) package outline drawing information top view bottom view pin a1 index detail : "a" side view dimension (inch) dimension (mm) symbol min nom max min nom max a -- -- 0.047 -- -- 1.20 a1 0.012 0.014 0.016 0.30 0.35 0.40 d 0.311 0.315 0.319 7.90 8.00 8.10 e 0.508 0.512 0.516 12.90 13.00 13.10 d1 -- 0.252 -- -- 6.40 -- e1 -- 0.433 -- -- 11.00 -- e1 -- 0.039 -- -- 1.00 -- e2 -- 0.031 -- -- 0.80 -- b 0.016 0.018 0.020 0.40 0.45 0.50 f -- 0.126 -- -- 3.20 --

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